What it is and the problem it solves
HBM solves the memory bandwidth wall in accelerators by replacing wide parallel buses with dense 3D-stacked interfaces.
Development began at AMD in 2008, to deal with the rising power use and physical size of computer memory. A team led by Senior AMD Fellow Bryan Black worked out the die-stacking problems, with SK Hynix as the memory partner, UMC for interposers, and Amkor Technology and ASE for packaging. SK Hynix built the first HBM chip in 2013, and the first GPU to use HBM was AMD’s Fiji, released in June 2015 as the Radeon R9 Fury X.
How it works
HBM stacks DRAM dies vertically using through-silicon vias (TSVs) to create a wide, short interconnect path between memory and processor.
A stack can hold up to 32 DRAM dies plus an optional base die with buffer circuitry and test logic, and HBM achieves higher bandwidth than DDR4 or GDDR5 with less power in a much smaller form factor. The width is the point. A first-generation stack of four dies has eight 128-bit channels, 1024 bits in total, so a GPU with four such stacks has a 4096-bit bus, against 32 bits for a GDDR chip. HBM1 ran at 1 GT/s per pin for 128 GB/s per package; HBM2 doubled the pin rate to 2 GT/s for 256 GB/s. Channels are independent and not necessarily synchronous with one another.
That many connections needed a new way of joining memory to processor. AMD and Nvidia both used purpose-built interposers, which also force memory and processor to sit physically close and so shorten memory paths. Semiconductor fabrication is significantly more expensive than printed circuit board manufacture, so the interposer adds to the price of the finished product.
What works
The JEDEC-standardised TSV-based stacking delivers predictable bandwidth scaling across generations—HBM2 (2016), HBM3 (2022), HBM4 (2025)—with increasing channel counts and transfer rates.
The standard has moved in steps. JEDEC adopted HBM in October 2013 as JESD235, after a 2010 proposal by AMD and SK Hynix, and accepted HBM2 in January 2016. A late-2018 update raised the per-stack figure to 307 GB/s and added 12-high stacks, for up to 24 GB. HBM3, announced on 27 January 2022, doubled the channel count from eight 128-bit channels to sixteen 64-bit channels, keeping 1024 data pins. In August 2022 Nvidia said its H100 would ship with five active HBM3 sites out of six on board, offering 80 GB and 3 TB/s. HBM4 followed in April 2025, with a 2048-bit interface, transfer speeds up to 8 Gb/s, total bandwidth up to 2 TB/s, stacks of 4 to 16 dies and capacities up to 64 GB; it is backwards compatible with HBM3 controllers. In July 2026 JEDEC published SPHBM4, which keeps HBM4 DRAM stacks but uses a 512-bit external interface at higher transfer rates, so HBM4-class bandwidth can be built on standard organic substrates without a silicon interposer.
What does not
HBM does not reduce memory latency meaningfully compared to conventional GDDR or DDR; it trades latency for raw bandwidth and area efficiency.
HBM is incompatible with Micron’s Hybrid Memory Cube interface, though similar to it in principle. Samsung’s lower-cost version, announced at Hot Chips in August 2016, removed the buffer die and cut the number of TSVs, at the expense of overall bandwidth (200 GB/s).
What it changes
It shifts memory bottlenecks from interface width to thermal management and package integration complexity.
Demand for HBM is unprecedented. One report found that DRAM prices in early 2026 had seen compounded increases, some exceeding 200% since early 2025, because of demand from the AI sector, with HBM crowding out commodity DRAM capacity. Micron notes a 3-to-1 conversion ratio between HBM and DDR5 wafer capacity, so every HBM ramp compresses general-purpose memory supply. In 2025 the largest HBM manufacturers were SK Hynix, Samsung Electronics and Micron Technology, and TSMC produces the base die.
Is it worth your time
Yes—if you design or deploy AI accelerators, GPUs, or high-performance compute systems where bandwidth density matters more than cost or power per bit.
