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Semiconductors · Hardware

Dynamic random-access memory

One transistor per bit bought memory density — and condemned every computer to perpetual housekeeping.

Worth your time?4.5/5Yes.Study the whole thing.What works, what does not, who it is for ↓
10:00in productionCh. 1 · The Density Trade/ 10:00 · ceiling 15 min
4 chapters · 10:00Ceiling 15:00

The brief is written and checked. The video joins this page when it is cut.4 chapters · 1 min read · 10:00 planned

Read the brief

DRAM is not elegant. It is a compromise made necessary by transistor cost and capacitor physics. It delivers density by accepting fragility — and forces every system built on it to schedule, arbitrate, and tolerate refresh.

Chapters & takeaways4
  1. 1:11
    The Density Trade

    One transistor and one capacitor per bit replaced six-transistor SRAM — cutting cost and area, not complexity.

  2. 2:50
    First Commercial DRAM

    Intel shipped the first working DRAM chip in 1970 — after five mask revisions to fix yield.

  3. 4:26
    Address Multiplexing

    Mostek’s 1973 MK4096 cut pin count by multiplexing row and column addresses — a layout trick still used today.

  4. 6:24
    The Refresh Tax

    Refresh is not optional: JEDEC mandates ≤64 ms per row, and reads only help — they don’t eliminate the need.

1 more chapterFewer chapters
Worth your time?

Yes. Study the whole thing.

4.5/ 5
What works
  • density
  • scalability
  • cost-per-bit
What does not
  • solve reliability
  • eliminate refresh
  • match SRAM speed
Study it if
  • hardware engineers
  • systems architects
  • performance analysts
Skip it if
  • application developers who assume memory is abstract
  • anyone expecting zero-overhead persistence
Who should study it, and who should skipHide who it is for
The written brief1 min read

What it is and the problem it solves

DRAM is a volatile semiconductor memory technology that trades storage stability for density. It solves the problem of building cheap, high-capacity RAM when transistors were expensive and silicon area was scarce.

How it works

Each DRAM cell stores one bit as charge on a capacitor, controlled by a single MOS transistor. Reading the cell discharges it slightly, so the sense amplifier must restore the charge — which doubles as refresh. Rows are refreshed every 64 ms or less, per JEDEC.

What works

The single-transistor, single-capacitor cell works. The Intel 1103 worked in 1970. Multiplexed addressing on the Mostek MK4096 worked in 1973. Sense-amplifier read-refresh works — reading a row refreshes all cells in that row.

What does not

It does not retain data without power. It does not avoid refresh overhead. It does not eliminate access latency: row activation and precharge add delay that SRAM avoids. It does not scale linearly — refresh cycles consume bandwidth and complicate timing.

What it changes

It changed memory economics. One transistor per bit cut cost and size versus six-transistor SRAM. It enabled kilobit-scale memory chips by 1970, then megabit and gigabit densities. It made volatile main memory affordable and scalable — at the cost of constant housekeeping.

Is it worth your time

Yes, if you work with memory systems, hardware design, or low-level performance optimisation. Its trade-offs — density over speed, simplicity over stability — still define how main memory behaves in every modern computer.

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