technologybriefs
9:20in productionCh. 1 · What '3D' actually means/ 9:20 · ceiling 15 min
Semiconductors · Hardware

Fin field-effect transistor

FinFETs don’t reinvent transistors — they reanchor them in physics when planar scaling fails.

The FinFET is a multigate MOSFET with gate(s) placed on two, three, or four sides of a fin-shaped channel, first fabricated in 1989 as the DELTA transistor; it reduces short-channel effects via dual-gate SOI structures; it delivers faster switching and higher current density than planar CMOS; its drive strength scales with fin count; and it is a non-planar, '3D' transistor.

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Chapters & takeaways4
  1. 1:00
    What '3D' actually means

    FinFETs are non-planar because the gate wraps around a vertical fin — not because they’re taller, but because charge control moves into the third dimension.

  2. 2:26
    Scaling by fin count

    Drive strength isn’t tuned with voltage or width — it’s set by counting fins under one gate.

  3. 4:01
    Why it switches faster

    Faster switching and lower leakage come from multi-sided gate coupling — not smaller features alone.

  4. 5:35
    Where the name came from

    The first FinFET was DELTA — fabricated in Japan in 1989 — and named for physical fins, not marketing.

Worth your time?

Yes. Study the whole thing.

4.5/ 5
What works
  • reduces short-channel effects in fully depleted SOI configurations
  • delivers faster switching and higher current density than planar CMOS
  • enables linear drive strength scaling via fin count
What does not
  • eliminate short-channel effects outright
  • deliver sub-5nm performance data
  • specify cost, yield or thermal density trade-offs
Study it if
  • semiconductor process engineers
  • device physicists
  • ASIC designers working at 16nm and below
Skip it if
  • software developers
  • AI model trainers
  • cloud infrastructure managers
The written brief1 min read

What it is and the problem it solves

The FinFET is a multigate MOSFET that solves short-channel effects in scaled CMOS by wrapping gate material around a raised silicon fin. It replaces planar transistors where leakage and threshold roll-off undermine reliability below ~20nm.

How it works

FinFETs are non-planar transistors with gates wrapped around fin-shaped silicon channels — two, three, or four sides, or fully surrounding the channel. A single transistor commonly contains multiple side-by-side fins under one gate, acting electrically as one unit. The fins form from the source/drain region on the silicon surface.

What works

FinFETs deliver significantly faster switching and higher current density than planar CMOS. Dual-gate SOI configurations demonstrably suppress short-channel effects. Drive strength scales predictably with fin count.

What does not

FinFETs do not eliminate short-channel effects outright. They reduce them significantly only when built as fully depleted SOI devices with dual-gate structures. The document gives no evidence of performance at sub-5nm nodes, nor of cost, yield, or thermal density trade-offs.

What it changes

FinFETs change how drive strength scales: it increases linearly with fin count, enabling precise performance binning without changing gate length or voltage. They shift transistor geometry from planar to 3D, forcing redesign of layout rules, parasitic extraction, and device modelling.

Is it worth your time

Yes — if you work on semiconductor design, process integration, or power-constrained logic scaling. It is not a general-purpose upgrade; it demands new lithography, epitaxy, and layout rules. Its value lies in predictable drive strength tuning and measurable short-channel suppression — not novelty.

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