technologybriefs
10:58in productionCh. 1 · Three states, one job/ 10:58 · ceiling 15 min
Hardware · Systems

MSI protocol

MSI isn’t elegant — it’s the minimal state machine that stops caches from lying to each other.

MSI is the minimal functional specification for cache coherency — a three-state machine that works, scales poorly, and remains essential to teach and reference.

HardwareSystemsComputingHardwareSemiconductorsComputing across the network →
Chapters & takeaways4
  1. 1:12
    Three states, one job

    MSI is defined by exactly three cache line states — Modified, Shared, Invalid — each assigning clear ownership and eviction duties.

  2. 3:43
    How reads and writes trigger traffic

    Read hits serve locally; write hits to Shared lines force broadcast invalidation — the core performance bottleneck.

  3. 5:20
    No boss, just rules

    Coherency emerges from pairwise state constraints and cache-to-cache signalling — not central coordination.

  4. 7:01
    Built, not imagined

    MSI was not theoretical — it mirrored the working protocol of the SGI 4D machine.

Worth your time?

Yes. Study the whole thing.

4/ 5
What works
  • guarantees memory consistency
  • enables local cache decisions
  • defines clear state responsibilities
What does not
  • scale beyond small core counts
  • eliminate broadcast traffic on write-to-shared
  • support ownership transfer without invalidation
Study it if
  • chip architects
  • verification engineers
  • computer architecture educators
Skip it if
  • application developers
  • cloud infrastructure operators
  • AI model trainers
The written brief1 min read

What it is and the problem it solves

MSI is a foundational cache-coherence protocol for multiprocessor systems. It solves the problem of ensuring all processors see a consistent view of memory when multiple caches hold copies of the same data.

How it works

MSI defines three cache line states — Modified, Shared, Invalid — and enforces transitions between them using inter-cache communication. On read hit in Modified or Shared state, the cache supplies data. On read miss (Invalid), it must first verify no other cache holds the block in Modified state. On write hit to a Shared block, it issues invalidation to other caches. Coherency is maintained via snooping or directory-based coordination between caches and the backing store.

What works

The three-state model cleanly separates responsibilities: Modified caches own write-back duty; Shared caches permit silent eviction; Invalid caches trigger fetch-and-validate. The protocol guarantees correctness for read/write hits and misses, provided caches obey the transition rules and communicate state changes.

What does not

MSI does not scale efficiently with core count. It requires broadcast invalidation on every Shared-to-Modified transition, generating bus traffic that grows with the number of caches. It offers no mechanism for ownership transfer without write-through or full invalidation, and no support for exclusive or forward states — limiting optimisation opportunities present in later protocols like MESI or MOESI.

What it changes

MSI changes how cache consistency is modelled: from ad hoc memory arbitration to a formally bounded state machine with explicit responsibilities per state. It establishes that coherency can be enforced by local cache decisions backed by global signalling — not centralised control — making distributed hardware verification possible.

Is it worth your time

Yes — if you design, verify, or debug multiprocessor cache subsystems. MSI is not a production protocol today, but its state machine is the conceptual foundation for understanding coherence trade-offs: simplicity versus bandwidth, correctness versus latency, and scalability versus broadcast cost.

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