11:21in productionCh. 1 · Co-design in hardware/ 11:21 · ceiling 15 min
Semiconductors · Hardware
FPGA prototyping
FPGA prototyping doesn’t prevent re-spins—it just moves the pain from silicon to the lab.
FPGA prototyping is a hardware verification method that maps SoC and ASIC designs onto FPGAs for real-time, pre-silicon validation. It enables concurrent hardware-software development and improves functional reliability over simulation alone. But it does not eliminate re-spins—nearly half are still caused by functional logic errors. It reduces time-to-market and avoids $20–40 million tape-out costs, yet demands deep expertise in partitioning, clock-domain crossing, and debugging. Tools like Certus and EXOSTIV address visibility gaps but are add-ons, not native capabilities. The value is real—but narrow, technical, and contingent on disciplined use.
One platform verifies hardware, firmware, and software before first silicon.
2:22
Reliability over simulation
Functional correctness is verified in real time—not in simulation.
3:44
Time and money saved
FPGAs ship in weeks; ASICs take six months—and cost $20–40 million.
5:02
The re-spin crisis
Two-thirds of SoCs fail first silicon—mostly due to logic errors FPGA prototyping targets.
6:28
What the toolchain hides
EDA software maps designs to FPGAs—but partitioning and clock domains remain hard.
7:56
Debugging is bolted on
Certus and EXOSTIV fix visibility bottlenecks—but they’re add-ons, not built-in.
Worth your time?
Yes. Study the whole thing.
4/ 5
What works
functional correctness validation
hardware-software co-verification
time-to-market reduction
re-spin risk mitigation
What does not
eliminate re-spins
make debugging trivial
remove need for simulation
Study it if
SoC architects
ASIC verification engineers
firmware developers working pre-silicon
Skip it if
software-only teams
low-complexity microcontroller projects
post-silicon validation teams
The written brief1 min read
What it is and the problem it solves
FPGA prototyping is a hardware verification method that runs SoC and ASIC designs on FPGAs prior to silicon fabrication. It solves the problem of catching functional logic errors late—when 67% of SoC designs fail first silicon and re-spins cost millions.
How it works
FPGA prototyping maps SoC and ASIC designs onto field-programmable gate arrays using EDA software. It enables hardware, firmware, and application software co-verification on a single platform before silicon tape-out.
What works
Running a SoC design on an FPGA prototype is functionally reliable—unlike simulation alone. A single platform verifies hardware, firmware, and application software pre-silicon. It reduces time-to-market and prevents revenue loss from missed market windows.
What does not
It does not eliminate re-spins. Nearly half of all re-spins are still caused by functional logic errors. Debugging remains constrained without advanced tools like Certus or EXOSTIV. Partitioning across multiple FPGAs introduces timing and resource-balancing overhead.
What it changes
It shifts verification left: hardware and software development run concurrently. It replaces simulation-only validation with real-time, cycle-accurate execution. It makes functional correctness testable at speed—before committing to six-month ASIC fabrication.
Is it worth your time
Yes—if you verify SoC or ASIC designs and face functional logic errors in first silicon. It cuts time-to-market and avoids $20–40 million tape-out costs—but demands expertise in partitioning, clock-domain crossing, and debug tooling.
